Nonvolatile semiconductor memory devices capable of preserving data even when they are powered OFF, such as EPROMs and EEPROMs, are roughly divided by charge storing means into two types; a flash memory type wherein hot electrons are injected into a floating gate, and a MIOS (Metal Insulator Oxide Semiconductor) type wherein electrons are injected into an insulating film utilizing a FN tunneling effect or direct tunneling effect. MIOS type memory devices include a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory device having a structure of metal-oxide film-nitride film-oxide film-semiconductor, a MNOS (Metal Nitride Oxide Semiconductor) having a structure of metal-nitride film-film oxide-semiconductor, and the like. The MIOS type memory device can be written more times by one to two figures than the flash type memory device and, hence, widely utilized.
With a memory cell of the MNOS type or MONOS type, however, if too many electrons are removed from an insulating film for trapping the electrons for erasing the data component stored in the cell, the threshold voltage would decrease too much, causing malfunction of the memory cell. In an attempt to solve this problem, there has been devised a semiconductor memory device of the composite type wherein a memory transistor of the MNOS type or MONOS type and a usual enhancement MOS transistor are formed in the same place.
FIGS. 13 and 14 each illustrate an example of a MNOS type memory cell of such a composite type. In the structure of the example illustrated in FIG. 13, a n.sup.+ -type source region 32 and n.sup.+ -type drain region 33 are formed in, as a whole, a p-type semiconductor substrate 31. A central part of a thick oxide film 35 formed on the substrate 31 is removed by etching. In the removed portion there are sequentially formed a thin oxide film 36 for tunneling, a film 37, for example, made of silicon nitride for trapping carriers and a gate electrode film 38, for example, made of polysilicon. The thin part of oxide film A realizes a memory part by tunneling electrons, while portions adjacent thereto are utilized as a usual enhancement MOS transistor.
In the structure of the example illustrated in FIG. 14, a silicon nitride film 37 for trapping carriers is etched so as to be formed on a memory part A only. This structure is for avoiding such a problem attributable to the former structure that with a gate insulating film composed of the thick silicon oxide film and silicon nitride film in the MOS transistor coexisting with the memory part A, the threshold voltage would be largely changed due to a bias temperature (BT) treatment for this transistor.
In fabrication of the memory cell illustrated in FIG. 14, however, it is necessary to carry out patterning for each of the thin oxide film for tunneling, nitride film and gate electrodes while taking into consideration an margin for alignment for each patterning and the length of each film. In addition, the gate electrodes need to be patterned so as to be positioned on the narrow gate insulating films present on the opposite sides of the memory part A. As a result, the channel length L cannot be shortened to less than 3 .mu.m. This leads to a limitation in scaling down a cell area and, hence, in increasing the integration density of devices.